The present invention relates to a multiple virtual storage control system for an electronic computer.
Modern electronic computer systems have adopted a multiple virtual storage system to realize efficient utilization of a central processor which is one of the resources of the system. Various attempts have also been made with regard to the central processor in order to realize a more efficient multiple virtual storage system.
In the virtual storage system, addresses of an instruction fetch and an operand fetch indicated by an instruction are recognized as logical addresses which do not correspond to a real storage. Accordingly, in referring to the storage, the logical address must be translated to a real address which corresponds to the real storage in one-to-one correspondence. The virtual storage represented by the logical address is divided into segments each of which is divided in pages each consisting of a predetermined number of bytes. The translation of the logical address to the real address is effected by referring to a translation table in the storage, which table comprises a segment table and a page table. The segment table is referred to by a sum of a first address of the segment table (hereinafter referred to as a Segment Table Origin address or STO address) and a segment address portion of the logical address. This entry includes a preset first address of the page table (hereinafter referred to as a Page Table Origin address or PTO address), and an entry of the page table which is a sum of the PTO address and a page address portion of the logical address is referred to. This latter entry includes a preset real address, which is linked to a byte address to determine the real address.
The above translation operation requires a large time because two tables in the storage must be referred to. As an approach to solve the problem, a high-speed address translator has been proposed. In this approach, a real address which has been determined by referring to the translation table in the storage is stored in the high-speed address translator in pair with the logical address so that when the same logical address of the storage is to be subsequently referred to, the corresponding real address is determined by the high-speed address translator. In this manner, the address translation operation can be effected at a higher speed.
In an electronic computer system capable of handling multiple virtual spaces, additional STO addresses are established to identify a plurality of virtual spaces triggered and virtual space numbers are assigned to the triggered virtual spaces. The virtual space numbers are stored in the high-speed address translator in one-to-one correspondence, which are used to examine the identity when the logical address is translated to the real address using the high-speed address translator.
The virtual space numbers are assigned using an STO address stack in which the STO address is stored. The STO address stack comprises a limited number of (e.g. four) registers each corresponding to a virtual space number. When a newly established STO address has not been stored in the STO address stack, this STO address is stored in any register, to thereby assign a virtual space number. In registering the address pair to the high-speed address translator, this virtual space number is also stored. When the address translation is requested, not only the identity between the logical address to be translated and the logical address in the translator but also the identity between the virtual space number being selected and the virtual space number stored in one-to-one correspondence with the address pair are examined to determine the real address.
In this manner, four STO addresses are stored in the STO address stack, and when an additional STO address is established it is stored in place of one of the previously registered STO addresses. Since the virtual space number for the old STO address which is now replaced by the new one is identical to the virtual space number for the newly stored STO address, it is necessary to cancel the address pair in the high-speed address translator, which was established based on the old STO address. This is carried out by examining if that virtual space number has been registered for all of the entries to the high-speed address translator and, if it has been registered, invalidating that entry. This cancellation operation is called virtual space purge. The virtual space purge requires checking of all of the entries in the high-speed address translator and hence a large amount of time is necessary. The necessity of the virtual space purge for each change of the virtual space lowers the performance of the electronic computer system. When the virtual space is changed, if the STO address has been registered in the STO address stack, only the virtual space number need be changed and the virtual space purge is not initiated.
The above-mentioned prior art is referred to in for example, U.S. Pat. No. 3,902,163 entitled "Buffered Virtual Storage and Data Processing System" by Gene M. Amdahl et al., and U.S. Pat. No. 3,781,808 entitled "Virtual Memory System" by Thomas P. Ahearn et al. Thus, in the prior art, the number of the virtual space number is equal to the number of the STO address stack registers and virtual space purge in the high-speed translator is effected by cancelling address translation pairs on one virtual space number at each time. Therefore, virtual space purge is performed every time of changeover of virtual space, thus lowering the performances of computer system.